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fedr44v064a-01 issue date: apr. 22, 2013 MR44V064A 64k(8,192-word ? 8-bit) feram (ferroelectric random access memory) 1/16 general description the MR44V064A is a nonvolatile 8,192-w ord x 8-bit ferroelectric random access memory (feram) developed in the ferroelectric process and s ilicon-gate cmos technology. the mr 44v064a is accessed using two-wire serial interface ( i2c bus ).unlike srams, this device, whose cells are nonvolatile, eliminates battery backup required to hold data. this device has no mechanisms of erasing and programming memory cells and blocks, such as those used for various eeproms. therefore, the wr ite cycle time can be equal to the read cycle time and the power consumption during a write can be reduced significantly. the MR44V064A can be used in various applications, because the device is guar anteed for the write/read tolerance of 10 12 cycles per bit and the rewrite co unt can be extended significantly. features ? 8,192-word ? 8-bit configuration i2c bus interface ? a single 3.3 v typ ? (2.5v to 3.6v) power supply ? operating frequency: 3.4mhz(max) hs-mode 400khz(max) f/s-mode ? read/write tolerance 10 12 cycles/bit ? data retention 10 years ? guaranteed operating temperature range ? 40 to 85 ? c (extended temperature version) ? package options: 8-pin plastic sop (p-sop8-200-1.27-t2k)
fedr44v064a-01 MR44V064A 2/16 pin configuration pin descriptions pin name description a0 ? a2 address ( input ) address pin indicates device address. when address value is match the device address code from sda, the device will be selected. the address pins are pulled down internally. sda serial data input serial data output ( input / output ) sda is a bi-directional line for i2c interface. the output driver is open-drain. a pull-up resistor is required. scl serial clock ( input ) serial clock is the clock input pin for setting for serial data timing. inputs are latched on the rising edge and outputs occur on the falling edge. wp write protect ( input ) write protect pin controls writ e-operation to the memory. when wp is high, all address in the memory will be protected. when wp is low, all address in the memory will be written. wp pin is pulled down internally. v cc , v ss power supply apply the specified voltage to v cc . connect v ss to ground. 8-pin plastic sop a0 a1 a2 vss vcc wp scl sda 1 8 2 7 3 6 4 5 MR44V064A
fedr44v064a-01 MR44V064A 3/16 i2c bus the MR44V064A employs a bi-directional two-wire i2c bus interface, works as a slave device. an example of i2c interf ace system with MR44V064A i2c bus comunication i2c bus data communication starts by start condition input, and ends by stop condition input. data is always 8bit long, acknowledge is always required after each by te. i2c bus carries out data transmission with plural devices connected by 2 communication lines of serial data ( sda ) and serial clock ( scl ). start condition before executing each command, start condition ( start bit ) where sda goes from ?high? down to ?low? when scl is ?high? is necessary. MR44V064A always detects whether sda and scl are in start condition ( start bit ) or not, therefore, unless this condition is satisfied, any command is executed. stop condition each command can be ended by sda rising from ?low? to ?high? when stop condition ( stop bit ), namely,scl is ?high?. scl sda start condition 1-7 8 9 1-7 8 9 1-7 8 9 stop condition address r/w ack data ack data ack scl sda pull-up resistor scl sda i2c bus master scl sda MR44V064A (slave) a2 a1 a0 0 0 0 scl sda MR44V064A (slave) a2 a1 a0 0 0 1
fedr44v064a-01 MR44V064A 4/16 acknowledge ( ack ) signal this acknowledge ( ack ) signal is a software rule to show whether data transfer has been made normally or not. in master and slave, the device ( -com at slave address input of write command, read command, and this ic at data output of read command) at the transmitter (sending) side releases the bus after output of 8bit data. the device (this ic at slave address input of write command, read command, and -com at data output of read command) at the receiver (receiving) side sets sda ?l ow? during 9 clock cycles , and outputs acknowledge signal ( ack signal) showing that it has received the 8bit data. this ic, after recognizing start condition and slave address (8bit), outputs acknowledge signal ( ack signal) ?low?. each write action outputs ac knowledge signal ( ack signal ) ?low?, at receiving 8bit data ( word address and write data ). each read action outputs 8bit data ( read data ), and detects acknowledge signal ( ack signal ) ?low?. when acknowledge signal ( ack signal ) is detect, and stop condition is not sent from the master ( -com) side, this ic continues data output. when acknowledge signal ( ack signal ) is not detected, this ic stops data transfer, and recognizes stop condition ( stop bit ), and ends read action. and this ic gets in status. slave address output slave address after st art condition from master. the significant 4 bits of slave address are used for recognizing a device type. the device code of this ic is fixed to ?1010?. next slave addresses (a2 a1 a0 ? device address) are for selecting devices, and plural ones can be used on a same bus according to the number of device addresses. the most insignificant bit (r/w?read/write) of slave ad dress is used for designating write or read action, and is as shown below. setting r/w to 0 write (setting 0 to word address setting of random read) setting r/w to 1 read write protect when wp terminal is set vcc(h level), data rewrite of all addresses is prohibited. when it is set vss(l level), data rewrite of all address is enabled. be sure to connect this terminal to vcc or vss, or control it to h level or l level. at extremely low voltage at power on / off, by setting the wp terminal ?h?, mistake write can be prevented. scl sda start condition 2 3 ack 56 89 7 4 1 12 1 0 0 1 a 2 a 1 a 0r/w
fedr44v064a-01 MR44V064A 5/16 command byte write cycle arbitrary data is written to feram. when to wr ite only 1 byte, byte write is normally used. start condition slave address with lsb is 0 (write) 1 st and 2 nd word address byte of write data. stop condition page write cycle when to write continuous data of 2 bytes or more, simultaneous write is possible by page write cycle. by page write cycle, up to 8,192 bytes data can be written. when data of the maximum bytes or higher is sent, data from the first byte is overwritten. current address read cycle current read cycle is a command to read data of internal address regist er without designating address, and is used when to verify just after write cycle. 1 0 a2 a1 a0 1 0 slave address s t a r t w r i t e 1 s t word address 2 n d word address w a 8 w a 7 w a 0 w a 12 d 7 d 0 s t o p a c k a c k a c k a c k write data 0 0 0 1 0 a2 a1 a0 1 0 slave address s t a r t r e a d read data d0 d7 s t o p n a c k a c k 1 0 a2 a1 a0 1 0 slave address s t a r t w r i t e 1 s t word address 2 n d word address w a 8 w a 7 w a 0 w a 12 d 7 d 0 s t o p a c k a c k a c k a c k d 7 d 0 a c k write data write data 0 0 0
fedr44v064a-01 MR44V064A 6/16 random read cycle random read cycle is a command to read data by designating address. start condition slave address with lsb is 0 (write) 1 st and 2 nd word address start condition slave address with lsb is 1 (read) read out byte of data. ack to ?h? stop condition sequential read cycle when ack signal ?l? after d0 is detected, and stop condition is not sent from master side, the next address data can be read in succession. current address read cycle ( hs-mode ) the MR44V064A support a 3.4mhz high speed mode. when hs-mode operation is needed, the hs-mode command is required before any command. after the hs-mode command is issued, MR44V064A will be the hs-mode, until stop condition is issued. byte write cycle ( hs-mode ) 1 0 a2 a1 a0 1 0 slave address s t a r t w r i t e 1 s t word address 2 n d word address w a 8 w a 7 w a 0 w a 12 d 7 d 0 s t o p a c k a c k a c k a c k write data 0 0 1 x x 0 0 hs-mode command s t a r t n a c k x 0 0 0 1 0 a2 a1 a0 1 0 slave address s t a r t w r i t e 1 s t word address 2 n d word address w a 8 w a 7 w a 0 w a 12 d 7 d 0 s t o p a c k a c k a c k read data 1 0 a2 a1 a0 10 slave address s t a r t r e a d a c k d 7 a c k d 0 n a c k 0 0 0 1 0 a2 a1 a0 1 0 slave address s t a r t w r i t e 1 s t word address 2 n d word address w a 8 w a 7 w a 0 w a 12 d 7 d 0 s t o p a c k a c k a c k read data 1 0 a2 a1 a0 10 slave address s t a r t r e a d a c k n a c k 0 0 0 0 0 1 x x 0 0 hs-mode command s t a r t read data d0 d7 s t o p n a c k n a c k 1 0 a2 a1 a0 1 0 slave address s t a r t r e a d a c k x
fedr44v064a-01 MR44V064A 7/16 electrical characteristics absolute maximum ratings the application of stress (voltage, current, or temperature) that exceeds the absolute maximum rating may damage the device. therefore, do not allow actual characteristics to exceed any one parameter ratings pin voltages rating parameter symbol min. max. unit note pin voltage (input signal) v in ?0.5 v cc + 0.5 v pin voltage (input/output voltage) v inq , v outq ?0.5 v cc + 0.5 v power supply voltage v cc ?0.5 4.0 v temperature range rating parameter symbol min. max. unit note storage temperature (extended temperature version) tstg ?55 125 c operating temperature (extended temperature version) topr ?40 85 c others ta=25c parameter symbol rating note power dissipation p d 1,000mw allowable input current i in +/- 20ma ta=25c allowable output current i out +/- 20ma ta=25c
fedr44v064a-01 MR44V064A 8/16 recommended operating conditions power supply voltage parameter symbol min. typ. max. unit note power supply voltage v cc 2.5 3.3 3.6 v ground voltage v ss 0 0 0 v dc input voltage parameter symbol min. max. unit note input high voltage v ih v cc x 0.7 v cc 0.3 v input low voltage v il ?0.3 v cc x 0.3 v
fedr44v064a-01 MR44V064A 9/16 dc characteristics dc input/output characteristics parameter symbol condition min. max. unit note output low voltage v ol i ol =2ma D 0.4 v input leakage current i li D ?10 10 a output leakage current i lo D ?10 10 a power supply current v cc =max.to min, ta=topr parameter symbol condition max. unit note power supply current (standby) i ccs scl,sda= v cc , a2,a1,a0= v cc or v ss 400 a power supply current (operating) i cca v in =0.3v or v cc 0.3v, fscl=3.4mhz fscl=400khz 1 600 ma ua
fedr44v064a-01 MR44V064A 10/16 ac characteristics v cc =max. to min., ta=topr. f/s-mode hs-mode parameter symbol min. max. min. max. unit note clock frequency f scl d.c. 400 dc 3400 khz clock low time tlow 1300 160 ns clock high time thigh 600 60 ns output data delay time taa 900 130 ns bus release time before transfer start tbuf 1300 300 ns start condition hold time thd:sta 600 160 ns start condition setup time tsu:sta 600 160 ns input data hold time thd:dat 0 0 ns input data setup time tsu:dat 100 10 ns sda, scl rise time tr 300 80 ns 1 sda, scl fall time tf 300 80 ns 1 stop condition setup time tsu:sto 600 160 ns output data hold time tdh 0 0 ns noise removal time (sda, scl) tsp 50 5 ns note: 1. not 100% tested equivalent ac load circuit 3.3v 1k ? out p ut 100pf
fedr44v064a-01 MR44V064A 11/16 timing scl sda (input) tr sda (output) tf tsu:dat tlow thigh tbuf taa tdh thd:dat 1/fscl tsp tsp tr tf scl sda (input) tsu:sta thd:sta tsu:sto start bit stop bit
fedr44v064a-01 MR44V064A 12/16 ? power-on and power-off characteristics (under recommended operating conditions) parameter symbol min. max. unit note power-on scl,sda high hold time t vhel 50 ? ? s 1, 2 power-off scl, sda high hold time t ehvl 100 ? ns 1 power-on interval time t vlvh 1 ? ? s 2 notes: 1. to prevent an erroneous operation, be sure to ma intain scl=sda="h", and se t the feram in an inactive state (standby mode) before and after power-on and power-off. 2. powering on at the intermediate voltage level will cau se an erroneous operation; thus, be sure to power up from 0 v. 3. enter all signals at the same time as power-on or enter all signals after power-on. ? p ower-on and power-off sequences 0 v v il max. v cc min. v cc v ih min. scl,sd a 0v v il max. v cc min. v cc v ih min. scl,sda t vhel t vlvh t ehvl
fedr44v064a-01 MR44V064A 13/16 read/write cycles and data retention (under recommended operating conditions) parameter min. max. unit note read/write cycle 10 12 ? cycle data retention 10 ? year capacitance signal symbol min. max. unit note input capacitance c in ? 10 pf 1 input/output capacitance c out ? 10 pf 1 note1: sampling value. measurement conditions are v in = v out = gnd, f = 1mhz, and ta = 25c
fedr44v064a-01 MR44V064A 14/16 package dimensions notes for mounting the surface mount type package the s urface mount type packages are ve ry susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact rohm?s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). (unit: mm)
fedr44v064a-01 MR44V064A 15/16 revision history page document no. date previous edition current edition description fedr44v064a-01 apr. 22, 2013 ? ? final edition 1
fedr44v064a-01 MR44V064A 16/16 notes no copying or reproduction of this document, in part or in whole, is permitted without the consent of lapis semiconductor co., ltd. the content specified herein is subject to change for improvement without notice. examples of application circuits, circuit constants an d any other information contained herein illustrate the standard usage and operations of the products. the peripheral conditions must be taken into account when designing circuits for mass production. great care was taken in ensuring the accuracy of the info rmation specified in this document. however, should you incur any damage arising from any inaccuracy or misprint of such information, lapis semiconductor shall bear no responsibility for such damage. the technical information specified herein is intended only to show the typical functions of and examples of application circuits for the products. lapis semiconductor does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or othe r rights held by lapis semiconductor and other parties. lapis semiconductor shall bear no responsibility whatso ever for any dispute arising from the use of such technical information. the products specified in this documen t are intended to be used with general-use electronic equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices). the products specified in this document are not designed to be radiation tolerant. while lapis semiconductor always makes efforts to enhance the quality and reliability of its products, a product may fail or malfunction for a variety of reasons. please be sure to implement in your equipment using the products safety measures to guard against the possibility of physical injury, fire or any other damage caused in the event of the failure of any product, such as derating, redundancy, fire control and fail-safe desi gns. lapis semiconductor shall bear no responsibility whatsoever for your use of any product outside of the prescribed scope or not in accordance with the instruction manual. the products are not designed or manufactured to be used with any equipment, device or system which requires an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of human injury (such as a me dical instrument, transpor tation equipment, aerospace machinery, nuclear-reactor controller, fuel-controller or other safety devi ce). lapis semiconductor shall bear no responsibility in any way for use of any of the products for the above special purposes. if a product is intended to be used for any such special purpose, pleas e contact a rohm sales representative before purchasing. if you intend to export or ship overseas any product or technology specified herein that may be controlled under the foreign exchange and the foreign trade law, you will be required to obtain a license or permit under the law. copyright 2013 lapis semiconductor co., ltd.

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